Exp 7 .JFET Amplifiers .CS and CD.



Discussion:

Why the dc load line for voltage-divider bias does not intersect with the origin of the transfer characteristic?
In a JFET with voltage-divider bias when ID=0, VGS is not Zero, as in the self-biased Case, because the voltage divider produces a voltage at the gate independent of the drain current. The voltage-divider dc load line is determined as follows.
For  EMBED Equation.3 

 EMBED Equation.3 

Therefore, one point on the line is at ID = 0 and VGS = VG.
Because of the value of ID=0 when VGS≠0

What is the type of biasing and the type of JFET channel for each of the following characteristic curves?.

Voltage driver bias Self-bias n-channel Voltage driver bias p-channel

In the CD amplifier, when Vgs is at its positive peak, at what points are Id and Vds? Explain why with the needed diagrams.



What factors determine the voltage gain of the common-source JFET amplifier?.

 EMBED Visio.Drawing.11 


CS JFET with external AC drain resistor

The ac voltage gain of this circuit is Vout/Vin where Vin=Vgs and Vout=Vds. the voltage gain expression is, therefore,

 EMBED Equation.3 


Where Rd=RD//RL , So factors are gm, Rd

Does RG affect on the biasing? Explain why. What is the purposes of RG?.

No does not effect.
The resistor RG serves two purposes:
Keeps the gate at approximately 0V dc because IGS is extremely small.
Having large value at AC (usually several mega ohms) which prevents loading at the AC signal source to keep the character at the JFET which has high input resistance.

Choose the correct answer:

There is 180o phase inversion between:
gate and drain voltage.
gate and source voltage.
source and drain voltage.
In a common-source amplifier, the output voltage is:
in phase with the input.
taken at the source.
taken at the drain.
If you are looking for both good voltage gain and high input resistance, you will use a:
CS amplifier.
CB amplifier.
CD amplifier.
For small-signal operation, an n-channel JFET must be biased at:
VGS=VGS(off).
-VGS(off) < VGS < 0 V.
0 V < VGS < +VGS(off).


The ideal maximum voltage gain of a CD amplifier is:
gmRs.
-gmRd.
1.
In a certain self-biased n-channel JFET circuit, ID=2mA and RS=1KΩ, VGS equal to:
2V.
-2V.
0V.

Experiment (7): JFET Amplifiers (CS and CD)

HYPER13PAGE HYPER15

3

Experiment No. (7)

JFET Amplifiers (CS and CD)

Id max

Vds min


2016/2015