8086 microprocessor L1

Intel 8086 (8088) Microprocessor Structure

What is a Computer?
Data Bus
Address Bus
Control Bus
Processor
Memory
I/O

8086 Microprocessor

Overview
Intel 8086 facts
8086
VCC (5V)
GND
CLK
20-bit address
16-bit data
  control signals To 8086
control signals from 8086
8086 signal classification
20 bit address bus allow accessing  1 M memory locations
16-bit external data bus. Thus, it need  one read (or write) operations to read (or write) a 16-bit data.


Organization of 8086
AH
AL
BH
BL
CH
CL
DH
DL
SP
BP
SI
DI
ALU
Flag register
Execution Unit (EU)
EU control
 CS
DS
SS
ES
ALU Data bus (16 bits)
Address bus (20 bits)
Instruction Queue
Bus control
External bus
IP
Data bus (16 bits)
Bus Interface Unit (BIU)
General purpose register
Segment register

* EU

EU (execution unit) of the 8086 tells the BIU where to fetch instructions or data from, decodes instructions, and executes instructions.

EU Operation

ALU Data bus (16 bits)
AH
AL
BH
BL
CH
CL
DH
DL
SP
BP
SI
DI
General purpose register
ALU
Flag register
EU control
instruction 1011000101001010
1. Fetch an instruction from instruction queue
2. According to the instruction, EU control logic generates control signals.  (This process is referred to as instruction decoding)
3. Depending on the control signal, EU performs one of the following  operations (Execution):
An arithmetic operation
A logic operation
Moving a data from a register
Changing flag register

1. General Purpose Registers

15
8
7
0
AX
BX
CX
DX
AH
AL
BH
BL
CH
CL
DH
DL
Accumulator
Base
Counter
Data
SP
BP
SI
DI
Data Group
Pointer and Index Group
Stack Pointer
Base Pointer
Source Index
Destination Index

2. Arithmetic Logic Unit (ALU)

n bits
n bits
A
B
Y
F
Carry
Y= 0 ?
A > B ?
F Y 0 0 0 A + B0 0 1A - B0 1 0A - 10 1 1A and B1 0 0A or B1 0 1 not A       Signal F control, which function will be conducted by ALU.
Signal F is generated according to the current instruction.
Basic arithmetic operations: addition, subtraction,  Basic logic operations: and, or, xor, shifting,

3. Flag Register

 ---
--------
OF
DF
IF
TF
ZF
SF
 AF
PF
CF
  0
15
Control Flags
Status Flags
IF: Interrupt enable flag DF: Direction flag TF: Trap flag
CF: Carry flag PF: Parity flag AF: Auxiliary carry flag ZF: Zero flag SF: Sign flag OF: Overflow flag
Flag register contains information reflecting the current status of a microprocessor. It also contains information which controls the operation of the microprocessor.


* BIU
BIU (bus interface unit) sends out addresses, fetches instructions from memory, reads data from ports and memory, and writes data to ports and memory. In other words, the BIU handles all transfers of data and addresses on the buses for the execution unit.

Memory Segmentation

A segment is a 64KB block of memory starting from any 16-byte boundary
For example: 00000, 00010, 00020, 20000, 8CE90, and E0840 are all valid  segment addresses
Segment registers in BIU
CS
SS
DS
ES
Code Segment
Data Segment
Stack Segment
Extra Segment
0
15
Offset is IP
Offset are Bx, SI, and DI
Offset is Bp, and Sp
Offset is DI

Generating Memory Addresses

How can a 16-bit microprocessor generate 20-bit memory addresses?
Segment (64K)
0000
+
16-bit register
16-bit register
20-bit memory address
00000
FFFFF
Left shift 4 bits
Intel 80x86 memory address generation
1M memory space
Offset
Segment address
Offset
Addr1
Addr1 + 0FFFF



Memory Address Calculation
Segment addresses must be stored  in segment registers
Offset is derived from the combination of pointer registers, the Instruction  Pointer (IP), and immediate values
0000
+
Segment address
Offset
Memory address
Examples
3
4
8
A
0
4
2
1
4
8
A
B
4
3
CS
IP
+
Instruction address
5
0
0
0
0
F
F
E
0
F
F
E
0
5
SS
SP
+
Stack address
1
2
3
4
0
0
0
2
2
2
3
6
2
1
DS
DI
+
Data address

Fetching Instructions

Where to fetch the next instruction?
CS
IP
1 2 3 4
0 0 1 2
1 2 3 5 2
12352
MOV AL, 0
8086
Memory
Update IP
After an instruction is fetched, Register IP is updated as follows:
IP = IP + Length of the fetched instruction
For Example: the length of MOV AL, 0 is 2 bytes. After fetching this instruction, the IP is updated to 0014

Instruction Machine Codes

Instruction machine codes are binary numbers
For Example:
0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0
MOV AL,04
MOV
Machine code structure
Opcode
Operand1
Opcode tells what operation is to be performed.  (EU control logic generates ALU control signals according to Opcode)
Register mode
Mode
Operand2
Mode indicates the type of a instruction: Register type, or Memory type