Experiment No. (4)
Bit Parity Generator Circuit
Objective:
Understanding the construction and applications of bit parity generators.
Introduction:
A bit parity, generated by the bit parity generator, usually accompanies the data
transmission process. The bit parity provides as a reference point and allows us to
compare and check whether the transmission process and the data transmitted are
correct or not.
There are two types of bit parity generators : The "Odd" & "Even" bit parity. The odd
parity is added to make the total number of 1s in the data an odd number . For
example "10111011" has six "1"s. When the bit parity is added to the end of this data,
The number
of
"1"s
in
the
data
will
become
an
'ODD "
number ,
hence the name "Odd
Parity Generator".
On the other hand,
an
"Even"
bit
parity
generator
will
add
a "1"
to
data
with
odd
number
of
"1"s
to
make
the
total
number
of
"1"s
even.
If
the
data
already
has
an
even
number
of
"1"s
no
bit
parity
"0" is
generated .
The output
Y
of
an "Even "
bit
parity
generator
is
shown
below.
Even
bit
parity
generator
circuit
EQUIPMENTS REQUIRED
KL - 31001 Digital Logic Lab, Module
KL
-
33003/4
PROCEDURES
(a) Bit Parity Generator Constructed With XOR Gates
1. Insert connection clip according to Fig.
4
-1 to construct the even bit parity
generator circuit of Fig.
4
-2.
Fig. 4-2: Even bit parity generator circuit
Fig. 4-1
2. Connect inputs A, B, C, D, E to DIP Switches 1.0-1.4 and output F6 to Logic Indicator
L1. Follow the input sequences in Table 4-1 and record the outputs.
Table 4-1
(b) Bit Parity Generator IC
Fig. 4-3
1. U7 on block d of module KL-33003 is a bit parity generator IC. Connect inputs A1, B1
C1, D1, E1, F1, G1, H1, I1 to DIP Switches 1.0 -1.7 & 2.0 respectively. Connect Y0
to L0, Y1 to L1, Follow the
input
sequences
given
in
Table
4
-2
and
record
the
outputs
INPUT
OUTPUT
E
D
C
B
A
F6
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
1
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
Active Low Output
Table 4-2
Exercise
1. Derive the circuits for a three-bit parity generator and four-bit parity checker
using an odd
INPUT
OUTPUT
I
H
G
F
E
D
C
B
A
y
0
y
1
(even) (odd)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
0
0
parity bit.
2. The most convenient way to construct a bit parity generator is with :
a) XOR Gates
b) AND Gates
c) OR Gates
3. If the data "11101001"
is
transmitted
with
bit
parity,
what
is
its
odd
bit
parity?
a) '1'
b) '0'
c) Neither
4. The purpose of generating bit parity is to:
a) protect signal
against
noise
b) detect transmission errors
c) increase data length
(c) Binary to Gray Code Converter
1. Insert connection clip according to Fig. 4-4 to construct three bit Binary to Gray Code Converter circuit.
2. Connect inputs B,C,D to SW3, SW2, SW1.
3. Connect Inputs A & E to logic zero so that the first and last X-OR gates work as buffers.
4. Connects outputs F2,F5,F6 to logic indicators L3,L2,L1
5. Follow the input sequences given in Table 4-3 to record the outputs.
Fig. 4-4
Table 4-3
(d) Gray Code to Binary Converter
1. Insert connection clip according to Fig. 4-5 to construct three bit Gray Code to Binary Converter circuit.
2. Connect inputs B,C,D to SW3, SW2, SW1.
3. Connect Inputs A & E to logic zero so that the first and last X-OR gates work as buffers.
4. Connects outputs F2,F5,F6 to logic indicators L3,L2,L1
5. Follow the input sequences given in Table 4-4 to record the outputs.
Fig. 4-5
Table 4-4