FET Characteristics



Study Objective:

Understanding the basic characteristics and symbols of JFET.

Introduction:

Bipolar transistors were covered in previous experiments. Now it is time to turn our attention to the second major transistor category, Field Effect Transistor (FET), FET is unipolar device because, unlike the bipolar transistor, it operates with only majority carriers (electrons or holes).
There are two main types of FETs: the Junction Field Effect Transistor (JFET) and the Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
Recall that the bipolar transistor is a current-control device; that is, the base current controls the amount of collector current. The FET is different: it is a voltage-control device. Where the voltage at one of terminals controls the amount of current through the device.
Depending on their structure, JFETs fall into either of two categories, n-channel or p-channel. Fig. 1(a) shows the basic structure of the n-channel JFET. Wire leads are connected to each end of the n-channel; the Drain is the upper end and the Source is at the lower end. Two p-type regions are diffuse in the n-type material to form a channel. and both p-type regions are connected to the Gate lead. In the remaining structure diagram, the interconnection of both p-type regions is omitted for simplicity, with a connection to only one shown. A p-channel JFET is shown Fig. 1(b). The reason of the name "Field Effect Transistor" is that the conductance between the Source and the Drain is controlled by electric field caused by the voltage applied to the Gate as we show later.
 EMBED Visio.Drawing.11 

(a): n-channel (b): p-channel
Fig. 1: Structure of the two types of JFET
Basic Operation:
To illustrate the operation of JFET, bias voltage are shown applied to an n-channel device in Fig. 2(a). VDD provide a drain-to-source voltage (VDS) and supplies current from drain to source (ID). VGG sets the reverse-bias voltage between the gate and the source (VGS), as shown.
The JFET is always operated with the gate-to-source pn junction reverse-bias. Reverse-biasing of the gate-source junction with a negative gate voltage produces a depletion region in the n-channel and thus increases its resistance (JFET has a very high input impedance). The channel width can be controlled by varying the gate voltage, and thereby, the amount of drain current, ID can also be controlled. This concept is illustrated in Fig. 2(b). The shaded areas represent the depletion region created by the reverse bias.
 EMBED Visio.Drawing.11 
 (a): JFET biased for conduction.

Fig. 2: Biased n-channel JFET and effect of VGG on channel width and ID

JFET Symbols:
The schematic symbols for both n-channel and p-channel JFET are shown in Fig. 3. Notice that the arrow on the gate points in for n-channel and out for p-channel.
Circuit symbols, D: Drain, G: Gate, S: Source.

 EMBED Visio.Drawing.11 


(a): n-channel (b): p-channel

Fig. 3: JFET Schematic SymbolsDrain Curves and pinch-off:

First consider the case where the gate to source voltage is 0 (VGS=0V). this is produced by shorting the gate to the source, as in Fig. 4(a). As VDD (and thus VDS) is increased from 0, ID will increase proportionally, as shown in the graph of the Fig. 4(b) between points A and B. in this region, the channel resistance is essentially constant because the depletion region is not large enough to have significant effect. This is called the ohmic region because VDS and ID are related by Ohm's law.
At point B, the curve levels off and ID becomes a relatively constant value called IDSS. It is at this point that the reverse-bias voltage across the gate-to-drain junction (VGD) produces a depletion region sufficient to narrow the channel so that its resistance begins to increase significantly. The values of VGD at this point is called Pinch-off voltage (VP). in this case where the gate bias voltage is zero, -VP=VDS at the point of pinch-off, because VDS and VGD are equal. In general, however,
 EMBED Equation.3 

Where VDS(P) is the pinch-off value of VDS for a given value of VGS.
VP is a constant value for a given JFET and represents a fixed parameter. The pinch-off value of VDS is a variable that depends on VGS.
Increasing VDS above point B produces an essentially constant ID equal to a specific value called IDSS (IDSS is the maximum value of ID when VGS=0). At point C, breakdown occurs and ID increases rapidly with irreversible damage to the device very likely. JFETs are always operated below the breakdown point and within the pinch-off region (between points B and C).
 EMBED Visio.Drawing.11 

(a): JFET with VGS=0V and (b): Drain Characteristic Curve with VGS=0V.
a Variable VDS.
Fig. 4: Generation of Drain Characteristic Curve.

VGS controls ID

Increasing negative value of VGS cause pinch-off to occur at successively lower values of VDS, resulting in lower values of ID, So, the amount of drain current is controlled by VGS. IDSS, the maximum drain current, occurs for VGS=0V, and decreases as VGS is made more negative (n-channel), as shown in Fig. 5. For a p-channel device, Positive values of VGS are required.
 EMBED Visio.Drawing.11 

(a): JFET biased at VGS=-1V (b): Family of Drain Characteristic Curves

Fig. 5: Pinch-off occurs at a lower VDS when VGS goes from 0V to -1V.


Cut-off
For an n-channel JFET, the more negative VGS is, the smaller ID in the pinch-off region becomes. When VGS is made sufficiently negative, ID is reduced to 0. this is caused by the widening of the depletion region to a point where it completely closes the channel. The value of VGS at the cut-off point is designed VGS(off). Equation (1) indicates that for any given n-channel JFET, cut-off occurs when VGS=VP. Since the pinch-off voltage is a constant for a given JFET, when VGS=VP the drain-to-source voltage VDS(P) must be 0. since there is no voltage drop between the drain and source, ID must be 0. Even through VDS may increase above 0V, ID remains essentially constant at near 0A. Cut-off is illustrated in Fig. 6.
 EMBED Visio.Drawing.11 

Fig. 6: JFET Action at Cut-off.

Transfer Characteristic

You have learned that a range of VGS values from 0 to VGS(off) controls the amount of drain current. For n-channel JFET, VGS(off) is negative, and for p-channel JFET, VGS(off) is positive.
Because VGS does control ID, the relationship between these two quantities is very important. Fig. 7 is a typical transfer characteristic curve which illustrates graphically the relationship between VGS and ID.
This curve, shows that the operating limits of a JFET are:
ID=0 when VGS=VGS(off).
ID= IDSS when VGS=0.
A JFET characteristic curve is actually parabolic in shape and can therefore be expressed mathematically as:
 EMBED Equation.3 


Fig. 7: JFET Transfer Characteristic Curve.

Experiment Equipments:
(1) KL-200 Linear Circuit Lab.
(2) Experiment Module: KL-23004.
(3) Experiment Instrument: 1. Multimeter or digital multimeter.
2. Power supply.
(4) Tools: Basic hand tools.
(5) Materials: As indicated in the KL-23004.


Experiment Items:
Item one (1): Experiment for Measurement for ldss.

1-1 Experiment Procedures:

Connect the circuit shown in Fig. 8
Connect ammeter to measure IDSS.
Connect G to ground and change Vdd from 3 to 18V then view the Id value indicated in ammeter, record your results as shown in table -1.
 EMBED Visio.Drawing.11 

Fig. 8

Table -1
VDD3V4V5V9V12V/15V20VIDSS(mA)

Item Two (2): Experiment for Measurement for lG.

2-1 Experiment Procedures:
Connect the circuit shown in Fig.
Connect ammeter to measure IG.
Connect +5V to VGS, and connect D, S to ground respectively. View the IG value, and record your results as shown in table -2.
Connect -5V to VGS, and connect D, S to ground respectively. View the IG value, and record your results as in table -2.


 EMBED Visio.Drawing.11 

Fig. 9

Table -2

VGSIG+5V-5VItem Three (3): Experiment for VP (VGS(off)) and the transfer characteristic.

3-1 Experiment Procedures:

Connect the circuit shown in Fig. 10 by using module KL-23004 block b.
Adjust VR4 (1MΩ) so that ID =0.
While ID =0, use Voltmeter to measure VGS (This represents VGS(off)).
Adjust VR4 (1MΩ) so that VGS will sequentially be (0V, -0.1V, -0.2V, -0.5V, -0.7V, -1V, -2V, -3V, -4V, -5V), Record each corresponding ID value as shown in table -3.
HYPER13 EMBED Visio.Drawing.11 

Fig. 10

Table -3

VGS0V-0.1V-0.2V-0.5V-0.7V-1V-2V-3V-4V-6V-8VID(mA)
4-1 Experiment Procedures:
Connect the circuit shown in Fig. 11.
At VGS=0V, Change VDD so that VDS will sequentially be (0.1V, 0.2V, 0.3V, 0.5V, 0.7V, 1V, 2V, 3V, 4V), Record each corresponding ID value in table 4.
Repeat step (2) at VGS= -0.5V, -1V, -1.5V, -2V. Record your results as shown in table -4. Fig. 11






Table -4

VGS=0V
VDS(v)0.10.20.30.50.7123456789ID(mA)
VGS=-0.5V
VDS(v)0.10.20.30.50.7123456789ID(mA)
VGS=-1V

VDS(v)0.10.20.30.50.7123456789ID(mA)

VGS=-1.5V
VDS(v)0.10.20.30.50.7123456789ID(mA)
VGS=-2V

VDS(v)0.10.20.30.50.7123456789ID(mA)

Conclution:(الاستنتاج)


Discussion:
Plot the transfer characteristic curve and drain characteristic curve from your results of item three.

Explain the meaning of Vp.

At what condition does cut-off occur? What is the state of the channel at the cut-off?

How does the VGS control drain current in JFET? Explain that.

What is the difference between ohmic region and pinch-off region in drain characteristic curve?

What is the different between bipolar and unipolar device? Explain that.

Why the JFET is called a voltage control device










Experiment): FET Characteristics

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Experiment FET Characteristics

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Experiment No. (9)

FET Characteristics


(b): Greater VGG narrows channel,
thus decreasing ID.

Ohmic Region

 EMBED Visio.Drawing.11 


 EMBED Visio.Drawing.11 


VGS (off)

 EMBED Visio.Drawing.11 


2N43914391

2N43914391

2N43914391

Vds